The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 01, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu-Cheng Chin, Hsinchu, TW;

Kong-Beng Thei, Pao-Shan Village, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 20/42 (2026.01); G01R 1/04 (2006.01); H10P 50/28 (2026.01); H10W 20/00 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
G01R 1/0416 (2013.01); H10P 50/28 (2026.01); H10W 20/069 (2026.01); H10W 20/42 (2026.01); H10W 70/685 (2026.01); H10W 90/701 (2026.01);
Abstract

Some embodiments relate to a method of an integrated circuit structure having a conductive structure for circuit probe testing. The method includes providing an integrated circuit structure including a substrate, a dielectric structure disposed over the substrate, and a plurality of electrodes disposed over an upper surface of the dielectric structure. The method also includes forming a first dielectric layer over the dielectric structure and the plurality of electrodes, etching the first dielectric layer over each of the plurality of electrodes, forming a conductive layer over the first dielectric layer and the plurality of electrodes, and removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes. Each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes.


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Chin, Shu-Cheng. (2026). Method of forming a plurality of conductive interconnect structures for circuit probe testing of an integrated circuit structure (U.S. Patent No. 12782386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12782386

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