The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2026
Filed:
Jan. 13, 2022
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Chien-Ju Chao, New Taipei City, TW;
Fang-Yu Fan, Hsinchu County, TW;
Yi-Chuin Tsai, Pingtung County, TW;
Kuo-Nan Yang, Hsinchu City, TW;
Chung-Hsing Wang, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile