The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Aug. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ta-Chun Lin, Hsinchu, TW;

Yu-San Chien, Hsinchu, TW;

Chun-Sheng Liang, Changhua, TW;

Kuo-Hua Pan, Hsinchu, TW;

Jhon Jhy Liaw, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/0165 (2025.01); H10D 84/038 (2025.01);
Abstract

Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium. The method includes performing a thermal treatment so that germanium atoms of the cladding layer are diffused into and reacted with the first semiconductor layer to form an intermixed layer, wherein the intermixed layer has a second atomic percentage of germanium that is less than the first atomic percentage of germanium. The method includes forming a gate electrode layer to surround each of the intermixed layers.


Find Patent Forward Citations

Lin, Ta-Chun. (2026). Semiconductor device having nanosheet transistor and methods of fabrication thereof (U.S. Patent No. 12777695). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777695

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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