The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Nov. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jie Chen, New Taipei City, TW;

Ying-Ju Chen, Yunlin County, TW;

Chen-Hua Yu, Hsinchu City, TW;

Der-Chyang Yeh, Hsinchu, TW;

Hsien-Wei Chen, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 90/00 (2026.01); H10W 70/00 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 70/654 (2026.01); H10W 70/655 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/00 (2026.01); H10W 90/22 (2026.01); H10W 90/28 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); H10W 20/42 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 72/0198 (2026.01); H10W 90/00 (2026.01); H10W 70/099 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 70/654 (2026.01); H10W 70/655 (2026.01); H10W 72/073 (2026.01); H10W 72/241 (2026.01); H10W 72/853 (2026.01); H10W 72/874 (2026.01); H10W 72/884 (2026.01); H10W 72/9413 (2026.01); H10W 74/00 (2026.01); H10W 90/22 (2026.01); H10W 90/28 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.


Find Patent Forward Citations

Chen, Jie. (2026). Redistribution layer structures for integrated circuit package (U.S. Patent No. 12772834). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772834

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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