The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Sep. 18, 2023
Qualcomm Incorporated, San Diego, CA (US);
Shreesh Narasimha, Charlotte, NC (US);
Yan Sun, San Diego, CA (US);
Yandong Gao, San Diego, CA (US);
Peijie Feng, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS S/D contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BM0 interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile