The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jul. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chi-Hsien Chung, New Taipei City, TW;

Tzu-Jui Wang, Fengshan City, TW;

Chia-Chi Hsiao, Tianzhong Township, TW;

Chen-Jong Wang, Hsin-Chu, TW;

Dun-Nian Yaung, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H04N 25/79 (2023.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/809 (2025.01); H04N 25/79 (2023.01); H10F 39/018 (2025.01); H10F 39/024 (2025.01); H10F 39/182 (2025.01); H10F 39/8053 (2025.01); H10F 39/8063 (2025.01); H10F 39/807 (2025.01); H10F 39/811 (2025.01);
Abstract

The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.


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Chung, Chi-Hsien. (2026). Image sensor integrated chip structure (U.S. Patent No. 12772592). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772592

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