The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Apr. 25, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Alexei Sadovnikov, Sunnyvale, CA (US);

Ming-Yeh Chuang, McKinney, TX (US);

Jingjing Chen, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/17 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10P 30/20 (2026.01); H10P 30/22 (2026.01); H10W 15/00 (2026.01);
U.S. Cl.
CPC ...
H10D 62/371 (2025.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10P 30/204 (2026.01); H10P 30/21 (2026.01); H10P 30/22 (2026.01); H10W 15/00 (2026.01); H10W 15/01 (2026.01);
Abstract

A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.


Find Patent Forward Citations

Sadovnikov, Alexei. (2026). Method of fabricating ldmos transistor with deep well implant through unmasked gate structure and a shallow well implant through masked gate structure (U.S. Patent No. 12772521). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772521

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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