The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Mar. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Ta-Chun Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A device includes a substrate, a first nanostructure device, a second nanostructure device, a dielectric fin, an isolation structure, and first and second dielectric gate structures. The substrate has a first device region, a second device region, and a connecting region. The first nanostructure device is over the first device region. The second nanostructure device is over the second device region. The dielectric fin is over the first device region and the connecting region and is in contact with a gate structure of the first nanostructure device. The isolation structure is over the second device region and is in contact with the second nanostructure device and the dielectric fin. The first dielectric gate structure is over the substrate and between the first device region and the connecting region. The second dielectric gate structure is over the substrate and between the second device region and the connecting region.


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Lin, Ta-Chun. (2026). Integrated circuit structure and manufacturing method thereof (U.S. Patent No. 12772512). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772512

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