The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jan. 04, 2023
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Mark I. Gardner, Cedar Creek, TX (US);

H. Jim Fulford, Marianna, FL (US);

Partha Mukhopadhyay, Oviedo, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/83 (2025.01); H10W 10/00 (2026.01); H10W 10/10 (2026.01); H10W 20/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6713 (2025.01); H10D 30/031 (2025.01); H10D 30/6728 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 84/83 (2025.01); H10W 10/011 (2026.01); H10W 10/10 (2026.01); H10W 20/056 (2026.01); H10W 20/062 (2026.01); H10W 20/089 (2026.01); H10W 20/092 (2026.01); H10W 90/00 (2026.01);
Abstract

A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.


Find Patent Forward Citations

Quick Actions:

Gardner, Mark. (2026). 3d field effect transistor (fet) device having u-shaped channel structure (U.S. Patent No. 12772496). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772496

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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