The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

May. 18, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Saravanan Sethuraman, Bayan Lepas, MY;

George Vergis, Portland, OR (US);

Tonia M. Rose, Wendell, NC (US);

John R. Goles, Folsom, CA (US);

John V. Lovelace, Driftwood, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/06 (2013.01);
Abstract

A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.


Find Patent Forward Citations

Sethuraman, Saravanan. (2026). Apparatus and method for per memory chip addressing (U.S. Patent No. 12769655). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769655

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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