Memory transaction timing compensation

Abstract

A memory subsystem with timing compensation for bandwidth recovery is disclosed. The memory subsystem includes a memory having and a memory controller coupled thereto via a memory bus. The memory controller is configured perform a write transaction that includes writing data to the memory circuit during ones of a plurality of write slots and determine, while performing the write transaction and based on an operating frequency of the memory bus, a number of idle write slots of the plurality of write slot during which data is not written to the memory. The memory controller is further configured to add a number of read slots corresponding to the number of idle write slots to a total number of read slots for a read transaction, and perform, upon completing the write transaction, a read transaction that includes reading data from the memory circuit during the total number of read slots.