The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Jul. 12, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Sergey Yuferev, Villach, AT;

Josef Höglauer, Kirchheim-Heimstetten, DE;

Gerhard Thomas Nöbauer, Villach, AT;

Hao Zhuang, Hohenbrunn, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/40 (2026.01); H10W 90/00 (2026.01); H10W 90/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/811 (2026.01); H10W 70/429 (2026.01); H10W 70/442 (2026.01); H10W 70/481 (2026.01); H10W 90/10 (2026.01);
Abstract

A semiconductor package includes low and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage contact pad and the third second lead provides the high voltage contact pad.


Find Patent Forward Citations

Yuferev, Sergey. (2026). Semiconductor package and method for fabricating a semiconductor package for upright mounting (U.S. Patent No. 12765436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765436

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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