The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Jul. 01, 2024
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Yong Liu, Cumberland Foreside, ME (US);

Yusheng Lin, Phoenix, AZ (US);

Liangbiao Chen, Scarborough, ME (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/04 (2026.01); H10W 70/40 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/04 (2026.01); H10W 70/451 (2026.01); H10W 70/457 (2026.01); H10W 70/479 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/01 (2026.01); H10W 90/811 (2026.01);
Abstract

Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.


Find Patent Forward Citations

Liu, Yong. (2026). Semiconductor packages and related methods (U.S. Patent No. 12765394). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765394

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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