The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Dec. 19, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Basoene Briggs, Heverlee, BE;

Boon Teik Chan, Wilsele, BE;

Juergen Boemmels, Heverlee, BE;

Assignee:

Imec VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 62/121 (2025.01); H10D 64/01318 (2026.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0177 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01); H10P 14/3411 (2026.01); H10P 14/3462 (2026.01);
Abstract

A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.


Find Patent Forward Citations

Briggs, Basoene. (2026). Method for forming a semiconductor device structure (U.S. Patent No. 12765040). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765040

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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