Memory controller communicating with vertically stacked dies and semiconductor device including the same

Abstract

A semiconductor device includes at least one core die and a logic die communicating with the core die via a plurality of through-silicon vias. The logic die includes a memory controller configured to control a memory operation of the core die and a PHY region configured to receive first input signals based on a first protocol from the memory controller and transmit first output signals generated based on the first input signals to the core die via the plurality of TSVs. The PHY region includes a protocol converter configured to perform alignment processing on bits of the first input signals so as to convert the protocol of the first input signals into a second protocol and then output the first input signals based on the second protocol, wherein the second protocol supports multi-phase communication between the PHY region and the core die.