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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12757796 B1

PDFFull Text
Date of Patent:
Oct. 06, 2026

Filed:

Mar. 25, 2024

Semiconductor package and method of manufacturing the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jeonggi Jin, Suwon-si, KR;

Gyuho Kang, Suwon-si, KR;

Unbyoung Kang, Suwon-si, KR;

Taehee Kim, Suwon-si, KR;

Hyungjun Park, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Attorney:

Fish & Richardson P.C.

Primary Examiner:

Monica D Harrison

Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 76/60 (2026.01); H10W 70/60 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/685 (2026.01); H10W 74/121 (2026.01); H10W 76/60 (2026.01); H10W 70/60 (2026.01); H10W 72/223 (2026.01); H10W 72/252 (2026.01); H10W 72/255 (2026.01); H10W 72/90 (2026.01); H10W 72/923 (2026.01); H10W 72/952 (2026.01); H10W 74/15 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes a semiconductor device including a substrate, bonding pads provided on a front surface of the substrate and bump structures provided on the bonding pads respectively, each of the bump structures having a metal pillar and a metal paste coated on one end portion of the metal pillar; and a wiring layer including a metal wiring layer having redistribution pads and a protective layer on the metal wiring layer and having recesses that expose at least portions of the redistribution pads. The semiconductor device is stacked on the wiring layer via the bump structures. Portions of the bump structures are respectively disposed in the recesses of the protective layer, and the metal pastes are respectively bonded to the redistribution pads.

Find Patent Forward Citations

Jin, Jeonggi. (2026). Semiconductor package and method of manufacturing the same (U.S. Patent No. 12757796). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12757796

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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