The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Oct. 26, 2023
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Michael Carroll, Jamestown, NC (US);

Eric K. Bolton, Kernersville, NC (US);

MA Shirley Asoy, High Point, NC (US);

XI Luo, High Point, NC (US);

Daniel Charles Kerr, Oak Ridge, NC (US);

Chi-Hsien Chiu, High Point, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 10/17 (2026.01); H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 70/66 (2026.01); H10W 72/20 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 70/66 (2026.01); H10W 72/242 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 72/922 (2026.01); H10W 72/9223 (2026.01); H10W 72/923 (2026.01); H10W 72/926 (2026.01); H10W 72/942 (2026.01); H10W 72/944 (2026.01); H10W 72/952 (2026.01); H10W 90/792 (2026.01);
Abstract

Embodiments of an IC device are disclosed. In some embodiments, an integrated circuit (IC) device, includes: an first active semiconductor layer that includes first active semiconductor device regions; a second active semiconductor layer that includes active semiconductor regions, the second active semiconductor layer being connected to the first active semiconductor layer and being positioned over the first active semiconductor layer; a first redistribution layer positioned over the second active conductor layer, the first redistribution layer is electrically connected to the first active semiconductor layer and the second active semiconductor layer; a passivation layer positioned on the first redistribution layer; a second redistribution layer positioned over the passivation layer, wherein the second redistribution layer is electrically connected to the first redistribution layer.


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