The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

May. 12, 2022
Applicant:

Zhuhai Access Semiconductor Co., Ltd., Guangdong, CN;

Inventors:

Xianming Chen, Guangdong, CN;

Lei Feng, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Wenshi Wang, Guangdong, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 40/22 (2026.01); H10W 70/68 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/50 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 40/22 (2026.01); H10W 70/68 (2026.01); H10W 72/247 (2026.01); H10W 72/50 (2026.01); H10W 72/07236 (2026.01); H10W 72/07252 (2026.01); H10W 72/07253 (2026.01); H10W 72/07254 (2026.01); H10W 72/221 (2026.01); H10W 72/227 (2026.01); H10W 72/234 (2026.01); H10W 72/237 (2026.01); H10W 72/926 (2026.01); H10W 72/9415 (2026.01); H10W 72/944 (2026.01); H10W 80/721 (2026.01); H10W 80/743 (2026.01); H10W 90/724 (2026.01);
Abstract

A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.


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