The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jul. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tzuan-Horng Liu, Taoyuan City, TW;

Hao-Yi Tsai, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 74/127 (2026.01); H10W 90/722 (2026.01); H10W 90/792 (2026.01);
Abstract

A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.


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