The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Apr. 23, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yen-Liang Chu, Hsinchu, TW;

Hung-Ju Li, Hsinchu City, TW;

Yi Ching Ong, Hsinchu, TW;

Kuo-Chyuan Tzeng, Chu-Pei City, TW;

Kuo-Ching Huang, Hsinchu City, TW;

Harry-Hak-Lay Chuang, Zhubei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); H10N 70/00 (2023.01); H10W 20/00 (2026.01); H10W 20/42 (2026.01); H10W 42/60 (2026.01);
U.S. Cl.
CPC ...
H10N 70/231 (2023.02); H10N 70/021 (2023.02); H10N 70/041 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02); H10N 70/8613 (2023.02); H10W 20/081 (2026.01); H10W 20/42 (2026.01); H10W 42/60 (2026.01);
Abstract

Dielectric material layers and an insulating layer may be formed over a semiconductor substrate containing a semiconductor region. A via opening may be etched through at least the insulating layer. A metal layer may be deposited and patterned to provide a heater element of a phase change memory (PCM) switch and an electrostatic discharge metal structure that fills the via opening. A phase change material layer may be deposited over the heater element and the electrostatic discharge metal structure. The phase change material layer may be patterned into a phase change material portion by performing an anisotropic etch process. An electrostatic discharge path including the electrostatic discharge metal structure and the doped semiconductor region discharges electrostatic charges that accumulate in the insulating layer into the semiconductor substrate during the anisotropic etch process.


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