The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Apr. 23, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wen-Li Chiu, Kaohsiung City, TW;

Chia-Hao Kuo, Taoyuan City, TW;

Fu-Hsiang Su, Hsinchu, TW;

Shih-Hsun Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2026.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01); H10W 10/20 (2026.01);
U.S. Cl.
CPC ...
H10D 84/0153 (2025.01); H10D 64/017 (2025.01); H10D 84/832 (2025.01); H10W 10/014 (2026.01); H10W 10/021 (2026.01); H10W 10/17 (2026.01); H10W 10/20 (2026.01);
Abstract

A semiconductor device includes a semiconductor substrate, a first device, a second device, and a composite isolation structure. The first device includes a first fin structure and a first gate structure. The first fin structure is disposed over the semiconductor substrate and includes a first channel region. The first gate structure wraps around the first channel region. The second device includes a second fin structure and a second gate structure. The second fin structure is disposed over the semiconductor substrate and includes a second channel region. The second gate structure wraps around the second channel region. The composite isolation structure is disposed between the first and second devices and includes first and second dielectric layers. The second dielectric layer is sandwiched between the semiconductor substrate and the first dielectric layer. A topmost surface of the second dielectric layer is lower than a bottom surface of the first channel region.


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