The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Dec. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron D. Lilak, Beaverton, OR (US);

Anh Phan, Beaverton, OR (US);

Rishabh Mehandru, Portland, OR (US);

Stephen M Cea, Hillsboro, OR (US);

Patrick Morrow, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Justin Weber, Portland, OR (US);

Salim Berrada, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/28 (2025.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/679 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/01326 (2026.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/689 (2025.01); H10D 84/85 (2025.01);
Abstract

Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.


Find Patent Forward Citations

Loading…