The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jan. 05, 2024
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Yu Hsuan Chang, New Taipei City, TW;

Ching-Wei Li, Hsinchu City, TW;

Jih San Lee, Hsinchu City, TW;

Tien-Hao Tang, Hsinchu City, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10D 62/102 (2025.01); H10D 62/116 (2025.01); H10D 62/126 (2025.01); H10D 62/151 (2025.01);
Abstract

A fully-isolated metal oxide semiconductor (MOS) device includes a substrate, an isolation well, a gate structure, a source region, a gradient region, a drain region, a first well, and an electro static discharge (ESD) protection region. The isolation well is formed in the substrate, and the gate structure is formed on the isolation well. The source region and the gradient region are formed in the isolation wells on both sides of the gate structure respectively, and the drain region is formed in the gradient region. The first well is formed below the drain region in the gradient region, and the ESD protection region is formed in the first well. The isolation well and the ESD protection region have a first conductivity type, and the gradient region and the first well have a second conductivity type.


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