The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Dec. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michael Goldsmith, Lake Oswego, OR (US);

Prashant Majhi, San Jose, CA (US);

Per Sverdrup, Redwood City, CA (US);

Chung-Ching Peng, Taipei, TW;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01); G06F 111/20 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01); G06F 2111/20 (2020.01); G06F 2119/18 (2020.01);
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.


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