The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Sep. 19, 2023
Applicant:

Monolithic Power Systems, Inc., Kirkland, WA (US);

Inventors:

Ting Ge, San Jose, CA (US);

Yingjiang Pu, Chengdu, CN;

Hunt Hang Jiang, Saratoga, CA (US);

Daocheng Huang, Santa Clara, CA (US);

Yuanfeng Zhou, San Jose, CA (US);

Qian Li, San Jose, CA (US);

Cong Deng, San Jose, CA (US);

Zhe Yang, San Jose, CA (US);

Wenyang Huang, Hangzhou, CN;

Assignee:

Monolithic Power Systems, Inc., Kirkland, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H01F 27/06 (2006.01); H01F 27/08 (2006.01); H01F 27/26 (2006.01); H01F 37/00 (2006.01); H10W 70/65 (2026.01); H10W 74/10 (2026.01); H10W 72/20 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H01F 27/06 (2013.01); H01F 27/08 (2013.01); H01F 27/266 (2013.01); H01F 37/00 (2013.01); H10W 70/65 (2026.01); H10W 74/114 (2026.01); H10W 72/227 (2026.01); H10W 72/232 (2026.01); H10W 72/237 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A power module, having a bottom substrate, a device substrate arranged on the bottom substrate and an inductor assembly arranged on the device substrate. The device substrate having a first power device chip and a second power device chip embedded within the device substrate. Each power device chip has a first surface and a second surface. The first surface of each power device chip is covered by a top heat layer, and the second surface of each power device chip has a plurality of pins or pads exposed on the second surface of the device substrate, and connected to the bottom substrate.


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