The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jul. 03, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunsoo Chung, Suwon-si, KR;

Younglyong Kim, Suwon-si, KR;

Inhyo Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/121 (2026.01); H10W 72/0198 (2026.01); H10W 72/07332 (2026.01); H10W 74/15 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/792 (2026.01);
Abstract

A semiconductor package includes: a buffer die; a first core die disposed on the buffer die; a second core die disposed on the first core die; a first non-conductive film (NCF) disposed between the first core die and the second core die and bonding the first core die and the second core die to each other; a first molding layer at least partially surrounding a side surface of the first core die; and a second molding layer surrounding the first NCF and the first molding layer, wherein the first core die, the second core die, and the buffer die are disposed on the second molding layer, wherein a side surface of the first molding layer and a side surface of the first NCF form a coplanar surface.


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