Semiconductor structure forming a plurality of transistors

Abstract

A semiconductor structure forming a plurality of transistors is disclosed. The semiconductor structure comprising: a source layer; a plurality of vertical nanowires erecting from the source layer; a first spacer layer arranged on the source layer and around each of the plurality of vertical nanowires; a gate layer arranged on the first spacer layer and around each of the plurality of vertical nanowires; a second spacer layer arranged on the gate layer and around each of the plurality of vertical nanowires; and a drain layer arranged on the second spacer layer and in contact with each of the plurality of vertical nanowires; wherein the gate layer comprises a first gate and a second gate each comprising a plurality of gate fingers, wherein the first gate comprises a first interconnecting gate portion interconnecting the gate fingers of the first gate, wherein the second gate comprises a second interconnecting gate portion interconnecting the gate fingers of the second gate, wherein the plurality of gate fingers of the first gate is interleaved with the plurality of gate fingers of the second gate, wherein the first gate is a gate of a first transistor and the second gate is a gate of a second transistor.