The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jun. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Te-Chih Hsiung, Taipei City, TW;

Peng Wang, Hsinchu, TW;

Huan-Just Lin, Hsinchu City, TW;

Jyun-De Wu, New Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/6729 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01);
Abstract

A device comprises source/drain epitaxial structures over a substrate; source/drain contacts over the source/drain epitaxial structures, respectively; a gate structure laterally between the source/drain contacts; a gate dielectric cap over the gate structure and having a bottom surface below top surfaces of the source/drain contacts; an oxide-based etch-resistant layer over the gate dielectric cap; a nitride-based etch stop layer over the oxide-based etch-resistant layer; an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and a gate contact extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch-resistant layer, and the gate dielectric cap to electrically connect with the gate structure.


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