Memory circuitry and methods used in forming memory circuitry

Abstract

Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A gate is operatively-proximate the channel region. A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The first capacitor electrode is directly electrically coupled to the first source/drain region. The second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. Digitlines extend elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. A wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. The wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. Methods are also disclosed.