The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2026
Filed:
Sep. 24, 2024
Cypress Semiconductor Corporation, San Jose, CA (US);
Ramakrishna Venigalla, Bengaluru, IN;
Partha Mondal, Paschim Medinipur, IN;
Rajesh Karri, Visakhapatnam, IN;
Yogendra Pratap Singh, Moradabad, IN;
Rushika Banam Balia Tudu, Bangalore, IN;
Gerhard Thomas Nöbauer, Villach, AT;
Arun Khamesra, Bangalore, IN;
Ankur Anchlia, Indore, IN;
Pulkit Shah, Bengaluru, IN;
Infineon Technologies Americas Corp., El Segundo, CA (US);
Abstract
Techniques for load current sensing in common-drain power FET switches are described. In an example embodiment, a power field effect transistor (FET) device includes back-to-back power FETs connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to use the sense voltage from the second replica FET to draw the sense current through the first replica FET.