The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Oct. 20, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Qi Xu, Wuhan, CN;

Chao Wang, Wuhan, CN;

Zhiyong Suo, Wuhan, CN;

Xuhui Wang, Wuhan, CN;

Zhen Xu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2026.01); H10W 20/20 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/15 (2026.01); H10W 80/00 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 74/117 (2026.01); H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 72/879 (2026.01); H10W 72/884 (2026.01); H10W 74/15 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/24 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01); H10W 90/792 (2026.01);
Abstract

Implementations of the present disclosure disclose a package structure, a fabricating method thereof, and a memory system. The package structure includes: a packaging substrate having a first surface and a second surface opposite the first surface; a semiconductor device on the first surface of the packaging substrate and coupled with the packaging substrate; and a cap layer covering the first surface and encapsulating the semiconductor device, wherein the cap layer and the packaging substrate have a total thickness in a first direction perpendicular to the first surface, and a ratio between a distance from an upper surface of the cap layer to an upper surface of the semiconductor device in the first direction and the total thickness satisfies a first preset value.


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