The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Feb. 21, 2023
Applicant:

Eliyan Corporation, Santa Clara, CA (US);

Inventor:

Ramin Farjadrad, Los Altos, CA (US);

Assignee:

Eliyan Corp., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2023.01); H10W 70/60 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2023.02); H10W 70/611 (2026.01); H10W 70/614 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/724 (2026.01);
Abstract

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip device including a first substrate having traces that are of a first connection density and a first chiplet formed via a first IC manufacturing process and coupled to the primary substrate traces. The first IC chip device also includes a second chiplet formed via a second IC manufacturing process that is different than the first IC manufacturing process. The second chiplet includes a first interface that is coupled to the first chiplet via the traces of the primary substrate. The second chiplet also includes a second interface that exhibits a second connection density that is lower than the first connection density. A second IC chip device is coupled to the first IC chip device via the second interface of the second chiplet. A second substrate is provided for mounting the first IC chip device and the second IC chip device.


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