The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

May. 13, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Clifford J. Engel, Hillsboro, OR (US);

Richard H. Livengood, San Jose, CA (US);

Mauro J. Kobrinsky, Portland, OR (US);

Robert L. Bristol, Portland, OR (US);

Akshit Peer, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01); H10W 70/63 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/427 (2026.01); H10W 20/023 (2026.01); H10W 20/20 (2026.01); H10W 70/635 (2026.01); H10W 72/00 (2026.01);
Abstract

Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.


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