The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Aug. 17, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Brandon P. Wirz, Taichung City, TW;

Sui Chi Huang, Taichung City, TW;

Youngrae Kim, Taichung City, TW;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/70 (2026.01); C09J 7/20 (2018.01); C09J 7/25 (2018.01); C09J 7/28 (2018.01); C09J 7/30 (2018.01); H10P 54/00 (2026.01);
U.S. Cl.
CPC ...
H10P 72/7402 (2026.01); C09J 7/20 (2018.01); C09J 7/25 (2018.01); C09J 7/28 (2018.01); C09J 7/30 (2018.01); H10P 54/00 (2026.01); C09J 2203/326 (2013.01); C09J 2203/366 (2020.08); C09J 2301/1242 (2020.08); C09J 2400/10 (2013.01); C09J 2400/143 (2013.01); C09J 2400/163 (2013.01); C09J 2479/086 (2013.01);
Abstract

Implementations described herein relate to a mount tape and methods of using the mount tape for semiconductor device manufacturing. The mount tape may include a first adhesive layer configured for release at a first stage of a semiconductor device manufacturing process, a second adhesive layer configured for release at a second stage of the semiconductor device manufacturing process, and an inner support layer positioned between the first adhesive layer and the second adhesive layer and configured for removal during the semiconductor device manufacturing process.


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