The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Feb. 07, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

PO-Lin Peng, Taoyuan City, TW;

Li-Wei Chu, Hsinchu City, TW;

Ming-Fu Tsai, Hsinchu City, TW;

Jam-Wem Lee, Hsinchu City, TW;

Yu-Ti Su, Tainan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); H10D 8/80 (2025.01); H10D 89/60 (2025.01); H10D 8/00 (2025.01); H10D 18/80 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/60 (2025.01); H10W 42/60 (2026.01); H10W 42/80 (2026.01);
U.S. Cl.
CPC ...
H10D 89/713 (2025.01); H10D 8/80 (2025.01); H10D 89/10 (2025.01); H10D 89/611 (2025.01); H10D 8/411 (2025.01); H10D 18/80 (2025.01); H10D 62/133 (2025.01); H10D 62/137 (2025.01); H10D 62/177 (2025.01); H10D 84/613 (2025.01); H10D 84/615 (2025.01); H10D 89/60 (2025.01); H10D 89/911 (2025.01); H10W 42/60 (2026.01); H10W 42/80 (2026.01);
Abstract

A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.


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