The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hidehiro Fujiwara, Hsinchu, TW;

Haruki Mori, Hsinchu, TW;

Wei-Chang Zhao, Hsinchu, TW;

Chia-Fu Lee, Hsinchu, TW;

Nail Etkin Can Akkaya, San Jose, CA (US);

Mahmut Sinangil, Campbell, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/57 (2006.01); G11C 11/413 (2006.01); G11C 11/419 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G06F 7/57 (2013.01); G11C 11/413 (2013.01); G11C 11/419 (2013.01); G11C 11/54 (2013.01);
Abstract

A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.


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