The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Sep. 25, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tong Suk Kim, Suwon-si, KR;

Sang Woong Lee, Suwon-si, KR;

Shle-Ge Lee, Suwon-si, KR;

Seung Soo Ha, Suwon-si, KR;

Chang Ui Hong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/65 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package, including a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region, a first semiconductor chip on an upper surface of the first structure, a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure, and a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip.


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