The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
May. 02, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Inventors:
Hiroki Noguchi, Hsinchu City, TW;
Yih Wang, Hsinchu City, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2026.01); H10W 20/20 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/685 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 90/722 (2026.01);
Abstract
A package structure may include a substrate, a plurality of dies on the substrate, and a memory bridge die including a first input/output structure connected to a first semiconductor die of the plurality of dies, and a second input/output structure connected to a second semiconductor die of the plurality of dies. The first semiconductor die may be connected to the second semiconductor die through the memory bridge die.