The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Mar. 16, 2022
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Ratndeep Srivastava, San Jose, CA (US);

Hui Gao, Fremont, CA (US);

Samantha Doan, Pleasanton, CA (US);

Ganesh Upadhyaya, Pleasanton, CA (US);

Gowri Channa Kamarthy, Pleasanton, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); C23C 16/455 (2006.01); H10P 14/60 (2026.01); H10P 14/694 (2026.01); H10P 50/26 (2026.01); H10P 50/28 (2026.01); H10P 70/00 (2026.01); H10P 72/00 (2026.01); H10W 20/43 (2026.01); H10W 20/47 (2026.01);
U.S. Cl.
CPC ...
H10B 12/0335 (2023.02); C23C 16/45544 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10P 14/6339 (2026.01); H10P 14/69433 (2026.01); H10P 50/268 (2026.01); H10P 50/283 (2026.01); H10P 70/27 (2026.01); H10P 72/0421 (2026.01); H10W 20/43 (2026.01); H10W 20/47 (2026.01);
Abstract

A method to electrically couple a capacitor to an active silicon region of a memory structure includes: providing a substrate including the memory structure; performing deposition and etch cycles to remove a portion of one or more dielectric layers from the substrate, enlarge a trench between adjacent bitline structures, and provide access to at least one of a polymer layer or a dielectric layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to remove the upper portion of the active silicon region to provide access for electrically coupling the capacitor to a remaining lower portion of the active silicon region. The over-etch operation is distinct from the breakthrough operation.


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