The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

May. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ping-Wei Wang, Hsin-Chu, TW;

Jui-Wen Chang, Hsinchu, TW;

Feng-Ming Chang, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01);
Abstract

A memory device includes a first pull-down (PD) transistor, a second PD transistor, a first pass-gate (PG) transistor, and a second PG transistor arranged in a first direction and share a first active area, and a first pull-up (PU) transistor, a second PU transistor, a first dielectric structure, and a second dielectric structure arranged in the first direction and share a second active area. The first dielectric structure and a third gate structure of the first PG transistor extend in the second direction and are aligned with each other in the second direction. The second dielectric structure and a fourth gate structure of the second PG transistor extend in the second direction and are aligned with each other in the second direction.


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