The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jan. 12, 2023
Applicant:

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventors:

Yong Chen, Singapore, SG;

David Gani, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 72/20 (2026.01); H10W 72/851 (2026.01); H10W 72/07253 (2026.01); H10W 72/234 (2026.01); H10W 72/853 (2026.01); H10W 90/00 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.


Find Patent Forward Citations

Quick Actions:

Chen, Yong. (2026). Semiconductor package with exposed electrical contacts (U.S. Patent No. 12733516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12733516

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