The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Oct. 09, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Steven M. Shank, Jericho, VT (US);

Richard J. Rassel, Essex Junction, VT (US);

John J. Ellis-Monaghan, Grand Isle, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 87/00 (2026.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/40 (2025.01); H10D 62/824 (2025.01); H10D 84/05 (2025.01); H10P 14/20 (2026.01); H10P 14/24 (2026.01); H10P 30/20 (2026.01); H10P 90/00 (2026.01); H10W 10/00 (2026.01); H10W 10/10 (2026.01);
U.S. Cl.
CPC ...
H10D 87/00 (2025.01); H10D 84/05 (2025.01); H10P 14/24 (2026.01); H10P 14/2907 (2026.01); H10P 90/1906 (2026.01); H10W 10/061 (2026.01); H10W 10/181 (2026.01); H10D 30/015 (2025.01); H10D 30/47 (2025.01); H10D 62/40 (2025.01); H10D 62/824 (2025.01); H10P 30/206 (2026.01); H10P 30/208 (2026.01);
Abstract

Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.


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