The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Feb. 06, 2024
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tetsuya Yoshida, Tokyo, JP;

Shibun Tsuda, Tokyo, JP;

Hideki Makiyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H10D 30/63 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2026.01); H10P 30/20 (2026.01); H10P 90/00 (2026.01); H10W 10/10 (2026.01);
U.S. Cl.
CPC ...
H10D 64/518 (2025.01); H10D 30/637 (2025.01); H10D 64/514 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10P 30/204 (2026.01); H10P 30/21 (2026.01); H10P 90/1906 (2026.01); H10W 10/181 (2026.01);
Abstract

A low withstand voltage MISFET and a high withstand voltage MISFET are formed on an SOI substrate. An ON operation and an OFF operation of the low withstand voltage MISFET are controlled by a first gate potential to be supplied to a first gate electrode and a back gate potential to be supplied to a first well region. An ON operation and an OFF operation of the high withstand voltage MISFET are controlled by a second gate potential to be supplied to a second gate electrode in a state where a second well region is electrically floating. An absolute value of a second power supply potential to be supplied to a second impurity region is larger than an absolute value of a first power supply potential to be supplied to a first impurity region.


Find Patent Forward Citations

Loading…