The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Jan. 10, 2024
United Microelectronics Corp., Hsin-Chu City, TW;
Tai-Cheng Hou, Tainan City, TW;
Da-Jun Lin, Kaohsiung City, TW;
Bin-Siang Tsai, Changhua County, TW;
Fu-Yu Tsai, Tainan City, TW;
Ya-Yin Hsiao, Taipei City, TW;
PO-Ching Su, Tainan City, TW;
Yi-Fan Li, Tainan City, TW;
Kuan-Jhih Hou, Chiayi County, TW;
Yu-Fu Wang, Taoyuan City, TW;
Ti-Bin Chen, Tainan City, TW;
Chih-Chiang Wu, Tainan City, TW;
Yao-Jhan Wang, Tainan City, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;
Abstract
A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.