Memory controller communicating with vertically stacked dies and semiconductor device including the same

Abstract

A semiconductor device includes at least one core die including a memory cell array, and a logic die configured to communicate with the at least one core die, the logic die includes first through fourth TSV circuit blocks including circuits each arranged in response to at least one TSV and configured to generate first through fourth output signals having different phases from each other, in which the first TSV circuit block generates the first output signal in synchronization with a first clock signal, the second TSV circuit block generates the second output signal in synchronization with a second clock signal, the third TSV circuit block generates the third output signal in synchronization with a clock signal obtained by inverting the first clock signal, and the fourth TSV circuit block generates the fourth output signal in synchronization with a clock signal obtained by inverting the second clock signal.