The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Dec. 05, 2023
Applicant:

Win Semiconductors Corp., Taoyuan City, TW;

Inventors:

Shao-Yu Tu, Taoyuan City, TW;

She-Hsin Hsiao, Taoyuan City, TW;

Jung-Tao Chung, Taoyuan City, TW;

Assignee:

WIN SEMICONDUCTORS CORP., Taoyuan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/90 (2026.01); H10W 72/20 (2026.01); H10W 72/29 (2026.01);
U.S. Cl.
CPC ...
H10W 72/90 (2026.01); H10W 72/20 (2026.01); H10W 72/221 (2026.01); H10W 72/232 (2026.01); H10W 72/252 (2026.01); H10W 72/29 (2026.01); H10W 72/923 (2026.01); H10W 72/932 (2026.01); H10W 72/934 (2026.01); H10W 72/9415 (2026.01); H10W 72/952 (2026.01);
Abstract

A semiconductor structure includes heterojunction bipolar transistors arranged in parallel and disposed on a substrate. The semiconductor structure also includes a landing structure disposed at the edge of the HBTs on the substrate. The semiconductor structure also includes wiring disposed on the HBTs and connected to the landing structure. The semiconductor structure also includes an insulating layer disposed on the landing structure and having a via. The semiconductor structure also includes a bump disposed on the top surface of the insulating layer and connected to the wiring through the via. The sidewall of the landing structure has a recess in a top view.


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