The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Jun. 21, 2023
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Te-Chih Hsiung, Taipei City, TW;
Jyun-De Wu, New Taipei City, TW;
Peng Wang, Hsinchu, TW;
Huan-Just Lin, Hsinchu City, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10D 30/62 (2025.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01); H10W 70/05 (2026.01);
U.S. Cl.
CPC ...
H10W 20/076 (2026.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10W 20/056 (2026.01); H10W 20/069 (2026.01); H10W 20/0698 (2026.01); H10W 20/081 (2026.01); H10W 20/42 (2026.01); H10W 20/432 (2026.01); H10W 70/095 (2026.01);
Abstract
A method includes forming a source/drain contact over a source/drain region. An ion implantation process is performed to form a doped region in a top of the source/drain contact. After the ion implantation process is performed, an interlayer dielectric (ILD) layer is deposited to cover the doped region of the source/drain contact. The ILD layer is etched to form a via opening exposing the source/drain contact. A source/drain via is filled in the via opening.