The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Feb. 17, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Ralf Otremba, Kaufbeuren, DE;

Christian Fachmann, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/811 (2026.01); H10W 70/466 (2026.01); H10W 70/481 (2026.01); H10W 72/073 (2026.01); H10W 72/865 (2026.01); H10W 72/868 (2026.01); H10W 72/884 (2026.01); H10W 72/886 (2026.01); H10W 74/111 (2026.01); H10W 90/00 (2026.01); H10W 70/465 (2026.01); H10W 72/30 (2026.01); H10W 72/871 (2026.01); H10W 90/755 (2026.01); H10W 90/767 (2026.01);
Abstract

A power semiconductor device includes: a package and a plurality of power semiconductor chips, each power semiconductor chip including a semiconductor body, a first load terminal, a second load terminal and a control terminal. The device also includes a plurality of outside terminals. The outside terminals include: one or more first outside terminals electrically connected with the first load terminals; one or more second outside terminals each of which is electrically connected with each of the second load terminals; and a plurality of third outside terminals. Each control terminal is electrically connected with at least one individual third outside terminal of the plurality of third outside terminals.


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