Techniques for protecting integrated circuitry from plasma-induced electrostatic discharge using a carrier substrate with junction features

Abstract

Techniques are provided for protecting integrated circuits from plasma-induced electrostatic discharge (ESD) using a carrier substrate with integrated junctions. According to some embodiments, the various metal features within an interconnect region above a plurality of semiconductor devices are electrically coupled to one or more conductive pads on a bonded carrier substrate. The conductive pads provide a contact to underlying doped regions within the carrier substrate that form one or more PN junctions. This provides the ability to electrically ground metal features in the interconnect region via the carrier substrate. Formation of additional interconnect layers such as those provided during far back end of line (FBEOL) processing, can proceed while causing less plasma-induced ESD damage to the integrated circuit, because the interconnect region is connected to ground of carrier substrate by way of PN junctions, thus providing a discharge path for charge that develops during subsequent processing.