The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Sep. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Yung-Shih Cheng, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

An integrated circuit device includes a transistor, a dielectric layer, a first vertical connecting structure. The transistor includes a gate structure. The dielectric layer surrounds the transistor. The first vertical connecting structure extends through the dielectric layer. The gate contact via is over the gate structure. The front-side metallization pattern is over the transistor. The front-side metallization pattern includes a first conductive path and a dummy conductive pattern. The first conductive path connects the gate contact via to a top end of the first vertical connecting structure. The dummy conductive pattern is connected to the first conductive path. The back-side metallization layer is below the transistor, wherein the back-side metallization layer is connected with a bottom end of the first vertical connecting structure.


Find Patent Forward Citations

Cheng, Yung-Shih. (2026). Integrated circuit device and manufacturing method thereof (U.S. Patent No. 12720837). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12720837

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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